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features ? high performance, low power atmel ? avr ? 8-bit microcontroller ? advanced risc architecture ? 131 powerful instructions ? most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 20 mips throughput at 20 mhz ? on-chip 2-cycle multiplier ? high endurance non-volatile memory segments ? 4/8/16kbytes of in-system self-programmable flash progam memory ? 256/512/512bytes eeprom ? 512/1k/1kbytes internal sram ? write/erase cycles: 10,000 flash/100,000 eeprom ? data retention: 20 years at 85c/100 years at 25c (1) ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-w rite operation ? programming lock for software security ? qtouch ? library support ? capacitive touch button s, sliders and wheels ? qtouch and qmatrix acquisition ? up to 64 sense channels ? peripheral features ? two 8-bit timer/counte rs with separate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? six pwm channels ? 8-channel 10-bit adc in tqfp and qfn/mlf package temperature measurement ? 6-channel 10-bit adc in pdip package temperature measurement ? programmable serial usart ? master/slave spi serial interface ? byte-oriented 2-wire se rial interface (philips i 2 c compatible) ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? six sleep modes: idle, adc noise reduction, power-save, power-down, standby, and extended standby ? i/o and packages ? 23 programmable i/o lines ? 28-pin pdip, 32-lead tqfp, 28-p ad qfn/mlf and 32-pad qfn/mlf ? operating voltage: ? 1.8 - 5.5v for atmega48p/88p/168pv ? 2.7 - 5.5v for atmega48p/88p/168p ? temperature range: ?-40 c to 85 c ? speed grade: ? atmega48p/88p/168pv: 0 - 4mhz @ 1.8 - 5.5v, 0 - 10mhz @ 2.7 - 5.5v ? atmega48p/88p/168p: 0 - 10mhz @ 2.7 - 5.5v, 0 - 20mhz @ 4.5 - 5.5v ? low power consumption at 1mhz, 1.8v, 25 c: ? active mode: 0.3ma ? power-down mode: 0.1a ? power-save mode: 0.8a (including 32khz rtc) note: 1. see ?data retention? on page 8 for details. 8-bit atmel microcontroller with 4/8/16k bytes in-system programmable flash atmega48p/v atmega88p/v atmega168p/v summary rev. 8025ms?avr?6/11
2 8025ms?avr?6/11 atmega48p/88p/168p 1. pin configurations figure 1-1. pinout atmega48p/88p/168p 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 (pcint19/oc2b/int1) pd3 (pcint20/xck/t0) pd4 gnd vcc gnd vcc (pcint6/xtal1/tosc1) pb6 (pcint7/xtal2/tosc2) pb7 pc1 (adc1/pcint9) pc0 (adc0/pcint8) adc7 gnd aref adc6 avcc pb5 (sck/pcint5) 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 (pcint21/oc0b/t1) pd5 (pcint22/oc0a/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 (pcint1/oc1a) pb1 (pcint2/ss/oc1b) pb2 (pcint3/oc2a/mosi) pb3 (pcint4/miso) pb4 pd2 (int0/pcint18) pd1 (txd/pcint17) pd0 (rxd/pcint16) pc6 (reset/pcint14) pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) tqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (pcint14/reset) pc6 (pcint16/rxd) pd0 (pcint17/txd) pd1 (pcint18/int0) pd2 (pcint19/oc2b/int1) pd3 (pcint20/xck/t0) pd4 vcc gnd (pcint6/xtal1/tosc1) pb6 (pcint7/xtal2/tosc2) pb7 (pcint21/oc0b/t1) pd5 (pcint22/oc0a/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) pc1 (adc1/pcint9) pc0 (adc0/pcint8) gnd aref avcc pb5 (sck/pcint5) pb4 (miso/pcint4) pb3 (mosi/oc2a/pcint3) pb2 (ss/oc1b/pcint2) pb1 (oc1a/pcint1) pdip 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 32 mlf top view (pcint19/oc2b/int1) pd3 (pcint20/xck/t0) pd4 gnd vcc gnd vcc (pcint6/xtal1/tosc1) pb6 (pcint7/xtal2/tosc2) pb7 pc1 (adc1/pcint9) pc0 (adc0/pcint8) adc7 gnd aref adc6 avcc pb5 (sck/pcint5) (pcint21/oc0b/t1) pd5 (pcint22/oc0a/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 (pcint1/oc1a) pb1 (pcint2/ss/oc1b) pb2 (pcint3/oc2a/mosi) pb3 (pcint4/miso) pb4 pd2 (int0/pcint18) pd1 (txd/pcint17) pd0 (rxd/pcint16) pc6 (reset/pcint14) pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) note: bottom pad should be soldered to ground. 1 2 3 4 5 6 7 21 20 19 18 17 16 15 28 27 26 25 24 23 22 8 9 10 11 12 13 14 28 mlf top view (pcint19/oc2b/int1) pd3 (pcint20/xck/t0) pd4 vcc gnd (pcint6/xtal1/tosc1) pb6 (pcint7/xtal2/tosc2) pb7 (pcint21/oc0b/t1) pd5 (pcint22/oc0a/ain0) pd6 (pcint23/ain1) pd7 (pcint0/clko/icp1) pb0 (pcint1/oc1a) pb1 (pcint2/ss/oc1b) pb2 (pcint3/oc2a/mosi) pb3 (pcint4/miso) pb4 pd2 (int0/pcint18) pd1 (txd/pcint17) pd0 (rxd/pcint16) pc6 (reset/pcint14) pc5 (adc5/scl/pcint13) pc4 (adc4/sda/pcint12) pc3 (adc3/pcint11) pc2 (adc2/pcint10) pc1 (adc1/pcint9) pc0 (adc0/pcint8) gnd aref avcc pb5 (sck/pcint5) note: bottom pad should be soldered to ground.
3 8025ms?avr?6/11 atmega48p/88p/168p 1.1 pin descriptions 1.1.1 vcc digital supply voltage. 1.1.2 gnd ground. 1.1.3 port b (pb7:0) xtal1/xtal2/tosc1/tosc2 port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. depending on the clock selection fuse settings, pb6 can be used as input to the inverting oscil- lator amplifier and input to the internal clock operating circuit. depending on the clock selection fuse settings, pb7 can be used as output from the inverting oscillator amplifier. if the internal calibrated rc osc illator is used as chip clock s ource, pb7:6 is used as tosc2:1 input for the asynch ronous timer/counter2 if th e as2 bit in assr is set. the various special features of port b are elaborated in ?alternate functions of port b? on page 80 and ?system clock and clock options? on page 27 . 1.1.4 port c (pc5:0) port c is a 7-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the pc5:0 output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port c pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. 1.1.5 pc6/reset if the rstdisbl fuse is programmed, pc6 is used as an i/o pin. note that the electrical char- acteristics of pc6 differ from those of the other pins of port c. if the rstdisbl fuse is unprogrammed, pc6 is used as a reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 29-3 on page 314 . shorter pulses are not guaran- teed to generate a reset. the various special features of port c are elaborated in ?alternate functions of port c? on page 83 . 1.1.6 port d (pd7:0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port d pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running.
4 8025ms?avr?6/11 atmega48p/88p/168p the various special features of port d are elaborated in ?alternate functions of port d? on page 86 . 1.1.7 av cc av cc is the supply voltage pin for the a/d converter, pc3:0, and adc7:6. it should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. note that pc6:4 use digital supply voltage, v cc . 1.1.8 aref aref is the analog reference pin for the a/d converter. 1.1.9 adc7:6 (tqfp and qfn/mlf package only) in the tqfp and qfn/mlf package, adc7:6 se rve as analog inputs to the a/d converter. these pins are powered from the analog supply and serve as 10-bit adc channels. 2. overview the atmega48p/88p/168p is a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the atmega48p/88p/168p achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consum ption versus processing speed.
5 8025ms?avr?6/11 atmega48p/88p/168p 2.1 block diagram figure 2-1. block diagram port c (7) port b (8) port d (8) usart 0 8bit t/c 2 16bit t/c 1 8bit t/c 0 a/d conv. internal bandgap analog comp. spi twi sram flash eeprom watchdog oscillator watchdog timer oscillator circuits / clock generation power supervision por / bod & reset vcc gnd program logic debugwire 2 gnd aref avcc data b u s adc[6..7] pc[0..6] pb[0..7] pd[0..7] 6 reset xtal[1..2] cpu
6 8025ms?avr?6/11 atmega48p/88p/168p the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. the atmega48p/88p/168p provides the following features: 4k/8k/16kbytes of in-system pro- grammable flash with read-while-wr ite capabilities, 256/512/512bytes eeprom, 512/1k/1kbytes sram, 23 general purpose i/o lines, 32 general purpose working registers, three flexible timer/counters with compare modes, internal and external interrupts, a serial pro- grammable usart, a byte-oriented, 2-wire serial interface, an spi serial port, a 6-channel 10- bit adc (8 channels in tqfp and qfn/mlf packages), a programmable watchdog timer with internal oscillator, and five so ftware selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, usart, 2-wire serial interface, spi port, and interrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscillator, disabling a ll other chip functions until the ne xt interrupt or hardware reset. in power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sl eeping. the adc noise reduction mode stops the cpu and all i/o modules except asynchronous time r and adc, to minimize switching noise dur- ing adc conversions. in standby mode, the crysta l/resonator osc illator is running while the rest of the device is sleeping. this allows very fa st start-up combined with low power consumption. atmel offers the qtouch ? library for embedding capacitive t ouch buttons, sliders and wheels functionality into avr microcontrollers. the patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes adjacent key suppression ? (aks ? ) technology for unambiguous detection of key events. the easy-to-use qtouch suite toolchain allows you to explore, develop and debug your own touch applications. the device is manufactured using atmel?s high density non-volatile memory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot pro- gram running on the avr core. the boot program can use any interface to download the application program in the applic ation flash memory. software in the boot flash section will continue to run while the application flash se ction is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel atmega48p/88p/168p is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the atmega48p/88p/168p avr is supported with a full suite of program and system develop- ment tools including: c compile rs, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
7 8025ms?avr?6/11 atmega48p/88p/168p 2.2 comparison between atme ga48p, atmega88p and atmega168p the atmega48p, atmega88p and atmega168p differ only in memory sizes, boot loader sup- port, and interrupt vector sizes. table 2-1 summarizes the different memory and interrupt vector sizes for the three devices. atmega88p and atmega168p support a real read-while-write self-programming mechanism. there is a separate boot loader section, and the spm instruction can only execute from there. in atmega48p, there is no read-while-write support and no separate boot loader section. the spm instruction can execute from the entire flash. table 2-1. memory size summary device flash eeprom ram interrupt vector size atmega48p 4kbytes 256bytes 512bytes 1 instruction word/vector atmega88p 8kbytes 512bytes 1kbytes 1 instruction word/vector atmega168p 16kbytes 512bytes 1kbyt es 2 instruction words/vector
8 8025ms?avr?6/11 atmega48p/88p/168p 3. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr. note: 1. 4. data retention reliability qualification results show that the pr ojected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 5. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructio ns that allow access to extended i/o. typically ?lds? and ?sts? combined with ? sbrs?, ?sbrc?, ?sbr?, and ?cbr?. 6. capacitive touch sensing the atmel ? qtouch ? library provides a simple to use solution to realize touch sensitive inter- faces on most atmel avr ? microcontrollers. the qtouch library includes support for the qtouch and qmatrix ? acquisition methods. touch sensing can be added to any application by linking the appropriate atmel qtouch library for the avr microcontroller. this is done by using a simple set of apis to define the touch chan- nels and sensors, and then calling the touch sens ing api?s to retrieve the channel information and determine the touch sensor states. the qtouch library is free and downloadable from the atmel website at the following location: www.atmel.com/qtouchlibrary . for implementation details and other information, refer to the atmel qtouch library user guide - also available for download from the atmel website.
9 8025ms?avr?6/11 atmega48p/88p/168p 7. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved ? ? ? ? ? ? ? ? (0xfe) reserved ? ? ? ? ? ? ? ? (0xfd) reserved ? ? ? ? ? ? ? ? (0xfc) reserved ? ? ? ? ? ? ? ? (0xfb) reserved ? ? ? ? ? ? ? ? (0xfa) reserved ? ? ? ? ? ? ? ? (0xf9) reserved ? ? ? ? ? ? ? ? (0xf8) reserved ? ? ? ? ? ? ? ? (0xf7) reserved ? ? ? ? ? ? ? ? (0xf6) reserved ? ? ? ? ? ? ? ? (0xf5) reserved ? ? ? ? ? ? ? ? (0xf4) reserved ? ? ? ? ? ? ? ? (0xf3) reserved ? ? ? ? ? ? ? ? (0xf2) reserved ? ? ? ? ? ? ? ? (0xf1) reserved ? ? ? ? ? ? ? ? (0xf0) reserved ? ? ? ? ? ? ? ? (0xef) reserved ? ? ? ? ? ? ? ? (0xee) reserved ? ? ? ? ? ? ? ? (0xed) reserved ? ? ? ? ? ? ? ? (0xec) reserved ? ? ? ? ? ? ? ? (0xeb) reserved ? ? ? ? ? ? ? ? (0xea) reserved ? ? ? ? ? ? ? ? (0xe9) reserved ? ? ? ? ? ? ? ? (0xe8) reserved ? ? ? ? ? ? ? ? (0xe7) reserved ? ? ? ? ? ? ? ? (0xe6) reserved ? ? ? ? ? ? ? ? (0xe5) reserved ? ? ? ? ? ? ? ? (0xe4) reserved ? ? ? ? ? ? ? ? (0xe3) reserved ? ? ? ? ? ? ? ? (0xe2) reserved ? ? ? ? ? ? ? ? (0xe1) reserved ? ? ? ? ? ? ? ? (0xe0) reserved ? ? ? ? ? ? ? ? (0xdf) reserved ? ? ? ? ? ? ? ? (0xde) reserved ? ? ? ? ? ? ? ? (0xdd) reserved ? ? ? ? ? ? ? ? (0xdc) reserved ? ? ? ? ? ? ? ? (0xdb) reserved ? ? ? ? ? ? ? ? (0xda) reserved ? ? ? ? ? ? ? ? (0xd9) reserved ? ? ? ? ? ? ? ? (0xd8) reserved ? ? ? ? ? ? ? ? (0xd7) reserved ? ? ? ? ? ? ? ? (0xd6) reserved ? ? ? ? ? ? ? ? (0xd5) reserved ? ? ? ? ? ? ? ? (0xd4) reserved ? ? ? ? ? ? ? ? (0xd3) reserved ? ? ? ? ? ? ? ? (0xd2) reserved ? ? ? ? ? ? ? ? (0xd1) reserved ? ? ? ? ? ? ? ? (0xd0) reserved ? ? ? ? ? ? ? ? (0xcf) reserved ? ? ? ? ? ? ? ? (0xce) reserved ? ? ? ? ? ? ? ? (0xcd) reserved ? ? ? ? ? ? ? ? (0xcc) reserved ? ? ? ? ? ? ? ? (0xcb) reserved ? ? ? ? ? ? ? ? (0xca) reserved ? ? ? ? ? ? ? ? (0xc9) reserved ? ? ? ? ? ? ? ? (0xc8) reserved ? ? ? ? ? ? ? ? (0xc7) reserved ? ? ? ? ? ? ? ? (0xc6) udr0 usart i/o data register 193 (0xc5) ubrr0h usart baud rate register high 197 (0xc4) ubrr0l usart baud rate register low 197 (0xc3) reserved ? ? ? ? ? ? ? ? (0xc2) ucsr0c umsel01 umsel00 upm01 upm00 usbs0 ucsz01 /udord0 ucsz00 / ucpha0 ucpol0 195/210
10 8025ms?avr?6/11 atmega48p/88p/168p (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 194 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 193 (0xbf) reserved ? ? ? ? ? ? ? ? (0xbe) reserved ? ? ? ? ? ? ? ? (0xbd) twamr twam6 twam5 twam4 twam3 twam2 twam1 twam0 ?242 (0xbc) twcr twint twea twsta twsto twwc twen ?twie 239 (0xbb) twdr 2-wire serial interface data register 241 (0xba) twar twa6 twa5 twa4 tw a3 twa2 twa1 twa0 twgce 242 (0xb9) twsr tws7 tws6 tws5 tws4 tws3 ?twps1twps0 241 (0xb8) twbr 2-wire serial interface bit rate register 239 (0xb7) reserved ? ? ? ? ? ? ? (0xb6) assr ? exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub 162 (0xb5) reserved ? ? ? ? ? ? ? ? (0xb4) ocr2b timer/counter2 output compare register b 160 (0xb3) ocr2a timer/counter2 output compare register a 160 (0xb2) tcnt2 timer/counter2 (8-bit) 160 (0xb1) tccr2b foc2a foc2b ? ? wgm22 cs22 cs21 cs20 159 (0xb0) tccr2a com2a1 com2a0 com2b1 com2b0 ? ?wgm21wgm20 156 (0xaf) reserved ? ? ? ? ? ? ? ? (0xae) reserved ? ? ? ? ? ? ? ? (0xad) reserved ? ? ? ? ? ? ? ? (0xac) reserved ? ? ? ? ? ? ? ? (0xab) reserved ? ? ? ? ? ? ? ? (0xaa) reserved ? ? ? ? ? ? ? ? (0xa9) reserved ? ? ? ? ? ? ? ? (0xa8) reserved ? ? ? ? ? ? ? ? (0xa7) reserved ? ? ? ? ? ? ? ? (0xa6) reserved ? ? ? ? ? ? ? ? (0xa5) reserved ? ? ? ? ? ? ? ? (0xa4) reserved ? ? ? ? ? ? ? ? (0xa3) reserved ? ? ? ? ? ? ? ? (0xa2) reserved ? ? ? ? ? ? ? ? (0xa1) reserved ? ? ? ? ? ? ? ? (0xa0) reserved ? ? ? ? ? ? ? ? (0x9f) reserved ? ? ? ? ? ? ? ? (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) reserved ? ? ? ? ? ? ? ? (0x9c) reserved ? ? ? ? ? ? ? ? (0x9b) reserved ? ? ? ? ? ? ? ? (0x9a) reserved ? ? ? ? ? ? ? ? (0x99) reserved ? ? ? ? ? ? ? ? (0x98) reserved ? ? ? ? ? ? ? ? (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) reserved ? ? ? ? ? ? ? ? (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x92) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) reserved ? ? ? ? ? ? ? ? (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) reserved ? ? ? ? ? ? ? ? (0x8d) reserved ? ? ? ? ? ? ? ? (0x8c) reserved ? ? ? ? ? ? ? ? (0x8b) ocr1bh timer/counter1 - output compare register b high byte 136 (0x8a) ocr1bl timer/counter1 - outp ut compare register b low byte 136 (0x89) ocr1ah timer/counter1 - output compare register a high byte 136 (0x88) ocr1al timer/counter1 - output compare register a low byte 136 (0x87) icr1h timer/counter1 - input capture register high byte 137 (0x86) icr1l timer/counter1 - input capture register low byte 137 (0x85) tcnt1h timer/counter1 - counter register high byte 136 (0x84) tcnt1l timer/counter1 - counter register low byte 136 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) tccr1c foc1a foc1b ? ? ? ? ? ?135 (0x81) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 134 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 ? ?wgm11wgm10 132 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
11 8025ms?avr?6/11 atmega48p/88p/168p (0x7f) didr1 ? ? ? ? ? ?ain1dain0d 247 (0x7e) didr0 ? ? adc5d adc4d adc3d adc2d adc1d adc0d 264 (0x7d) reserved ? ? ? ? ? ? ? ? (0x7c) admux refs1 refs0 adlar ? mux3 mux2 mux1 mux0 260 (0x7b) adcsrb ?acme ? ? ? adts2 adts1 adts0 263 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 261 (0x79) adch adc data register high byte 263 (0x78) adcl adc data register low byte 263 (0x77) reserved ? ? ? ? ? ? ? ? (0x76) reserved ? ? ? ? ? ? ? ? (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) reserved ? ? ? ? ? ? ? ? (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) timsk2 ? ? ? ? ? ocie2b ocie2a toie2 161 (0x6f) timsk1 ? ?icie1 ? ? ocie1b ocie1a toie1 137 (0x6e) timsk0 ? ? ? ? ? ocie0b ocie0a toie0 109 (0x6d) pcmsk2 pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 72 (0x6c) pcmsk1 ? pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 72 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pc int4 pcint3 pcint2 pcint1 pcint0 72 (0x6a) reserved ? ? ? ? ? ? ? ? (0x69) eicra ? ? ? ?isc11isc10isc01isc00 69 (0x68) pcicr ? ? ? ? ? pcie2 pcie1 pcie0 (0x67) reserved ? ? ? ? ? ? ? ? (0x66) osccal oscillator calibration register 38 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr prtwi prtim2 prtim0 ? prtim1 prspi prusart0 pradc 43 (0x63) reserved ? ? ? ? ? ? ? ? (0x62) reserved ? ? ? ? ? ? ? ? (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 38 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 55 0x3f (0x5f) sreg i t h s v n z c 10 0x3e (0x5e) sph ? ? ? ? ? (sp10) 5. sp9 sp8 13 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 13 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) reserved ? ? ? ? ? ? ? ? 0x39 (0x59) reserved ? ? ? ? ? ? ? ? 0x38 (0x58) reserved ? ? ? ? ? ? ? ? 0x37 (0x57) spmcsr spmie (rwwsb) 5. ? (rwwsre) 5. blbset pgwrt pgers selfprgen 289 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr ? bods bodse pud ? ? ivsel ivce 45/66/90 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf 55 0x33 (0x53) smcr ? ? ? ?sm2sm1sm0se 41 0x32 (0x52) reserved ? ? ? ? ? ? ? ? 0x31 (0x51) reserved ? ? ? ? ? ? ? ? 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 245 0x2f (0x4f) reserved ? ? ? ? ? ? ? ? 0x2e (0x4e) spdr spi data register 173 0x2d (0x4d) spsr spif wcol ? ? ? ? ? spi2x 172 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 171 0x2b (0x4b) gpior2 general purpose i/o register 2 26 0x2a (0x4a) gpior1 general purpose i/o register 1 26 0x29 (0x49) reserved ? ? ? ? ? ? ? ? 0x28 (0x48) ocr0b timer/counter0 output compare register b 0x27 (0x47) ocr0a timer/counter0 output compare register a 0x26 (0x46) tcnt0 timer/counter0 (8-bit) 0x25 (0x45) tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 ? ?wgm01wgm00 0x23 (0x43) gtccr tsm ? ? ? ? ? psrasy psrsync 141/163 0x22 (0x42) eearh (eeprom address register high byte) 5. 22 0x21 (0x41) eearl eeprom address register low byte 22 0x20 (0x40) eedr eeprom data register 22 0x1f (0x3f) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 22 0x1e (0x3e) gpior0 general purpose i/o register 0 26 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
12 8025ms?avr?6/11 atmega48p/88p/168p note: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specif ied bit, and can therefore be used on regi sters containing such status flags. the cbi and sbi instructions work wit h registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x 20 must be added to these addresses. the atmega48p/88p/168p is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o spac e from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 5. only valid for atmega88p/168p. 0x1d (0x3d) eimsk ? ? ? ? ? ?int1int0 70 0x1c (0x3c) eifr ? ? ? ? ? ? intf1 intf0 70 0x1b (0x3b) pcifr ? ? ? ? ? pcif2 pcif1 pcif0 0x1a (0x3a) reserved ? ? ? ? ? ? ? ? 0x19 (0x39) reserved ? ? ? ? ? ? ? ? 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) tifr2 ? ? ? ? ? ocf2b ocf2a tov2 161 0x16 (0x36) tifr1 ? ?icf1 ? ? ocf1b ocf1a tov1 138 0x15 (0x35) tifr0 ? ? ? ? ? ocf0b ocf0a tov0 0x14 (0x34) reserved ? ? ? ? ? ? ? ? 0x13 (0x33) reserved ? ? ? ? ? ? ? ? 0x12 (0x32) reserved ? ? ? ? ? ? ? ? 0x11 (0x31) reserved ? ? ? ? ? ? ? ? 0x10 (0x30) reserved ? ? ? ? ? ? ? ? 0x0f (0x2f) reserved ? ? ? ? ? ? ? ? 0x0e (0x2e) reserved ? ? ? ? ? ? ? ? 0x0d (0x2d) reserved ? ? ? ? ? ? ? ? 0x0c (0x2c) reserved ? ? ? ? ? ? ? ? 0x0b (0x2b) portd portd7 portd6 portd 5 portd4 portd3 portd2 portd1 portd0 91 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 91 0x09 (0x29) pind pind7 pind6 pi nd5 pind4 pind3 pind2 pind1 pind0 91 0x08 (0x28) portc ? portc6 portc5 portc4 portc3 portc2 portc1 portc0 90 0x07 (0x27) ddrc ? ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 90 0x06 (0x26) pinc ? pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 90 0x05 (0x25) portb portb7 portb6 portb 5 portb4 portb3 portb2 portb1 portb0 90 0x04 (0x24) ddrb ddb7 ddb6 ddb 5 ddb4 ddb3 ddb2 ddb1 ddb0 90 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 90 0x02 (0x22) reserved ? ? ? ? ? ? ? ? 0x01 (0x21) reserved ? ? ? ? ? ? ? ? 0x0 (0x20) reserved ? ? ? ? ? ? ? ? address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page
13 8025ms?avr?6/11 atmega48p/88p/168p 8. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp (1) k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call (1) k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2
14 8025ms?avr?6/11 atmega48p/88p/168p brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 mnemonics operands description operation flags #clocks
15 8025ms?avr?6/11 atmega48p/88p/168p note: 1. these instructions are only available in atmega168p. pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks
16 8025ms?avr?6/11 atmega48p/88p/168p 9. ordering information 9.1 atmega48p note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see figure 29-1 on page 312 and figure 29-2 on page 312 . 4. tape & reel speed (mhz) power supply (v) ordering code (2) package (1) operational range 10 (3) 1.8 - 5.5 atmega48pv-10au atmega48pv-10aur (4) atmega48pv-10mmu atmega48pv-10mmur (4) atmega48pv-10mu atmega48pv-10mur (4) atmega48pv-10pu 32a 32a 28m1 28m1 32m1-a 32m1-a 28p3 industrial (-40 c to 85 c) 20 (3) 2.7 - 5.5 atmega48p-20au atmega48p-20aur (4) atmega48p-20mmu atmega48p-20mmur (4) atmega48p-20mu atmega48p-20mur (4) atmega48p-20pu 32a 32a 28m1 28m1 32m1-a 32m1-a 28p3 package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 28m1 28-pad, 4 x 4 x 1.0 body, lead pitch 0.45mm quad flat no-lead/micro lead frame package (qfn/mlf) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip)
17 8025ms?avr?6/11 atmega48p/88p/168p 9.2 atmega88p note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see figure 29-1 on page 312 and figure 29-2 on page 312 . 4. taper & reel. speed (mhz) power supply (v) ordering code (2) package (1) operational range 10 (3) 1.8 - 5.5 atmega88pv-10au atmega88pv-10aur (4) atmega88pv-10mu atmega88pv-10mur (4) atmega88pv-10pu 32a 32a 32m1-a 32m1-a 28p3 industrial (-40 c to 85 c) 20 (3) 2.7 - 5.5 atmega88p-20au atmega88p-20aur (4) atmega88p-20mu atmega88p-20mur (4) atmega88p-20pu 32a 32a 32m1-a 32m1-a 28p3 package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf)
18 8025ms?avr?6/11 atmega48p/88p/168p 9.3 atmega168p note: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering infor mation and minimum quantities. 2. pb-free packaging complies to the european directive for re striction of hazardous substa nces (rohs directive).also halide free and fully green. 3. see figure 29-1 on page 312 and figure 29-2 on page 312 . 4. taper & reel. speed (mhz) (3) power supply (v) ordering code (2) package (1) operational range 10 1.8 - 5.5 atmega168pv-10au atmega168pv-10aur (4) atmega168pv-10mu atmega168pv-10mur (4) atmega168pv-10pu 32a 32a 32m1-a 32m1-a 28p3 industrial (-40 c to 85 c) 20 2.7 - 5.5 atmega168p-20au atmega168p-20aur (4) atmega168p-20mu atmega168p-20mur (4) atmega168p-20pu 32a 32a 32m1-a 32m1-a 28p3 package type 32a 32-lead, thin (1.0mm) plastic quad flat package (tqfp) 28p3 28-lead, 0.300? wide, plastic dual inline package (pdip) 32m1-a 32-pad, 5 x 5 x 1.0 body, lead pitch 0.50mm quad flat no-lead/micro lead frame package (qfn/mlf)
19 8025ms?avr?6/11 atmega48p/88p/168p 10. packaging information 10.1 32a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 3 2a, 32-lead, 7 x 7 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) c 32a 2010-10-20 pin 1 identifier 0~7 pin 1 l c a1 a2 a d1 d e e1 e b notes: 1. this package conforms to jedec reference ms-026, variation aba. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 8.75 9.00 9.25 d1 6.90 7.00 7.10 note 2 e 8.75 9.00 9.25 e1 6.90 7.00 7.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ common dimen s ion s (unit of measure = mm) s ymbol min nom max note
20 8025ms?avr?6/11 atmega48p/88p/168p 10.2 28m1 title drawing no. gpc rev. packa g e drawin g contact: packagedra w ings@atmel.com 2 8 m1 zb v b 2 8 m1, 28-pad, 4 x 4 x 1.0 mm body, lead pitch 0.45 mm, 2.4 x 2.4 mm exposed pad, thermally enhanced plastic very thin quad flat no lead package (vqfn) 10/24/0 8 s ide view pin 1 id bottom view top view n ote: the terminal #1 id is a laser-marked feat u re . d e e k a1 c a d2 e2 y l 1 2 3 b 1 2 3 0.45 common dimen s ion s (unit of meas u re = mm) s ymbol min nom max note a 0. 8 0 0.90 1.00 a1 0.00 0.02 0.05 b 0.17 0.22 0.27 c 0.20 ref d 3.95 4.00 4.05 d2 2.35 2.40 2.45 e 3.95 4.00 4.05 e2 2.35 2.40 2.45 e 0.45 l 0.35 0.40 0.45 y 0.00 ? 0.0 8 k 0.20 ? ? r 0.20 0.4 ref (4x)
21 8025ms?avr?6/11 atmega48p/88p/168p 10.3 32m1-a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 3 2m1-a , 32-pad, 5 x 5 x 1.0 mm body, lead pitch 0.50 mm, e 32m1-a 5/25/06 3.10 mm exposed pad, micro lead frame package (mlf) common dimen s ion s (unit of measure = mm) s ymbol min nom max note d1 d e1 e e b a3 a2 a1 a d2 e2 0.08 c l 1 2 3 p p 0 1 2 3 a 0.80 0.90 1.00 a1 ? 0.02 0.05 a2 ? 0.65 1.00 a3 0.20 ref b 0.18 0.23 0.30 d d1 d2 2.95 3.10 3.25 4.90 5.00 5.10 4.70 4.75 4.80 4.70 4.75 4.80 4.90 5.00 5.10 e e1 e2 2.95 3.10 3.25 e 0.50 bsc l 0.30 0.40 0.50 p ? ? 0.60 ? ? 12 o note: jedec standard mo-220, fig. 2 (anvil singulation), vhhd-2. top view s ide view bottom view 0 pin 1 id pin #1 notch (0.20 r) k 0.20 ? ? k k
22 8025ms?avr?6/11 atmega48p/88p/168p 10.4 28p3 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 28p3 , 28-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) b 28p3 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb b2 (4 places) common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.5724 a1 0.508 ? ? d 34.544 ? 34.798 note 1 e 7.620 ? 8.255 e1 7.112 ? 7.493 note 1 b 0.381 ? 0.533 b1 1.143 ? 1.397 b2 0.762 ? 1.143 l 3.175 ? 3.429 c 0.203 ? 0.356 eb ? ? 10.160 e 2.540 typ note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
23 8025ms?avr?6/11 atmega48p/88p/168p 11. errata 11.1 errata atmega48p the revision letter in this section refers to the revision of the atmega48p device. 11.1.1 rev. c no known errata. 11.1.2 rev. b no known errata. 11.1.3 rev. a not sampled. 11.2 errata atmega88p the revision letter in this section refers to the revision of the atmega88p device. 11.2.1 rev. c not sampled. 11.2.2 rev. b no known errata. 11.2.3 rev. a no known errata. 11.3 errata atmega168p the revision letter in this section refers to the revision of the atmega168p device. 11.3.1 rev b no known errata. 11.3.2 rev a no known errata.
24 8025ms?avr?6/11 atmega48p/88p/168p 12. datasheet revision history please note that the referring page numbers in th is section are referred to this document. the referring revision in this section are referring to the document revision. 12.1 rev. 8025m-06/11 12.2 rev. 8025l-07/10 12.3 rev. 8025k-10/09 12.4 rev. 8025j-05/09 12.5 rev. 8025i-02/09 12.6 rev. 8025h-02/09 1. added atmel qtouch librar y support and qtouch sens ing capability features. 2. updated ?ordering information? to include tape and reel devices. 3. updated the datasheet with atmel new style guide. 1. removed from the front page, the note ?not recommended for new design?. 2. editorial updates. 1. updated ?low frequency cr ystal oscillator? with the table 9-8 on page 33 . 2. editorial updates. 1. removed the ?about? section. 2. removed atmega328p device and its reference from the data sheet. 3. editorial updates. 1. removed ?preliminary? from atmega48p/88p/168p. 1. added power-save maximum values and footnote to ?atmega48p dc characteris- tics? on page 310 . 2. added power-save maximum values and footnote to ?atmega88p dc characteris- tics? on page 311 . 3. added power-save maximum values and footnote to ?atmega168p dc characteris- tics? on page 311 . 4. added power-save maximum values and footnote to ?? on page 312 . 5. added errata for revision a, ?? on page 23 .
25 8025ms?avr?6/11 atmega48p/88p/168p 12.7 rev. 8025g-01/09 12.8 rev. 8025f-08/08 12.9 rev. 8025e-08/08 1 atmega48p/88p not recommended for new designs. 2. updated the footnote note1 of the table 9-3 on page 30 . 3. updated the table 9-5 on page 31 by removing a footnote note1. 4. updated the table 9-11 on page 34 by removing a footnote note1. 5. updated the footnote note1 of the table 9-13 on page 35 . 6. updated the footnote note2 of the ?atmega48p dc characteristics? on page 310 and removed tbd from the table. 7. updated the footnote note2 of the ?atmega88p dc characteristics? on page 311 and removed tbd from the table. 8. updated the footnote note2 of the ?atmega168p dc characteristics? on page 311 and removed tbd from the table. 9. updated the footnote note2 of the ?? on page 312 and removed tbd from the table. 10. updated the footnote note1 of the table 29-4 on page 314 . 11. replaced the figure 30-69 on page 358 by a correct one. 12. replaced the figure 29-173 on page 419 by a correct one. 13. updated ?errata? on page 23 . 14. updated ?mcucr ? mcu control register? on page 44 . 15. updated ?tccr2b ? timer/counter control register b? on page 159 . 1. updated ?register summary? on page 9 with power-save numbers. 2. added atmega328p ?standby supply current? on page 408 . 1. updated description of ?stack pointer? on page 13 . 2. updated description of use of external capacitors in ?low frequency crystal oscilla- tor? on page 33 . 3. updated table 9-10 in ?low frequency crystal oscillator? on page 33 . 4. added note to ?address match unit? on page 220 . 5. added section ?reading the signature row from software? on page 283 . 6. updated ?program and data memory lock bits? on page 291 to include atmega328p in the description. 7. added ?? on page 312 . 8. updated ?speed grades? on page 312 for atmega328p. 9. removed note 6 and 7 from the table ?2-wire serial interface characteristics? on page 317 . 10. added figure ?minimum reset pu lse width vs. v cc .? on page 346 for atmega48p. 11. added figure ?minimum reset pu lse width vs. v cc .? on page 370 for atmega88p. 12. added figure ?minimum reset pu lse width vs. v cc .? on page 394 for atmega168p. 13. added ?register summary? on page 9 . 14. updated ordering information for ?packaging information? on page 19 .
26 8025ms?avr?6/11 atmega48p/88p/168p 12.10 rev. 8025d-03/08 12.11 rev. 8025c-01/08 12.12 rev. 8025b-01/08 12.13 rev. 8025a-07/07 1. updated figures in ?speed grades? on page 312 . 2. updated note in table 29-4 in ?system and reset characteristics? on page 314 . 3. ordering codes for ?packaging information? on page 19 updated. - atmega328p is offered in 20 mhz option only. 4. added errata for atmega328p rev. b, ?? on page 23 . 1. power-save maximum values removed form ?atmega48p dc characteristics? on page 310 , ?atmega88p dc characteristics? on page 311 , and ?atmega168p dc characteristics? on page 311 . 1. updated ?features? on page 1 . 2. added ?data retention? on page 8 . 3. updated table 9-2 on page 29 . 4. removed ?low-frequency crystal oscillator internal load capacitance? table from ?low frequency crystal oscillator? on page 33 . 5. removed jtd bit from ?mcucr ? mcu control register? on page 45 . 6. updated typical and general program setup for reset and interrupt vector addresses in ?interrupt vectors in atmega168p? on page 63 and ?interrupt vectors in atmega328p? on page 65 . 7. updated interrupt vectors start address in table 12-5 on page 64 and table 11-7 on page 66 . 8. updated ?temperature measurement? on page 259 . 9. updated atmega328p ?fuse bits? on page 292 . 10. removed v ol3 /v oh3 rows from ?dc characteristics? on page 309 . 11. updated condition for v ol in ?dc characteristics? on page 309 . updated max value for v il2 in ?dc characteristics? on page 309 . 12. added ?atmega48p dc characteristics? on page 310 , ?atmega88p dc characteris- tics? on page 311 , and ?atmega168p dc characteristics? on page 311 . 13. updated ?system and reset characteristics? on page 314 . 14. added ?atmega48p typical characteristics? on page 322 , ?atmega88p typical characteristics? on page 346 , and ?atmega168p typical characteristics? on page 370 . 15. updated note in ?instruction set summary? on page 13 . 1. initial revision.
8025ms?avr?6/11 atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel : (+1)(408) 441-0311 fax : (+1)(408) 487-2600 www.atmel.com atmel asia limited unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel : (+852) 2245-6100 fax : (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel : (+49) 89-31970-0 fax : (+49) 89-3194621 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel : (+81)(3) 3523-3551 fax : (+81)(3) 3523-7581 ? 2011 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, avr ? , qtouch ? , qmatrix ? , avr studio ? and others are registered trademarks or trade- marks of atmel corporation or its subsidiaries. windows ? and others are registered trademarks of microsoft corporation in u.s. and other countries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in connection wi th atmel products. no license, ex press or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its pro ducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purp ose, or non-infringement. in no even t shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitati on, damages for loss and prof- its, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or com- pleteness of the contents of th is document and reserves the right to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information cont ained herein. unless specifically provided otherwise, atmel pr oducts are not suit- able for, and shall not be used in, automotive applications. atme l products are not intended, authorized, or warranted for use as components in applica- tions intended to support or sustain life.

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